Many electronic devices need to convert the various physical phenomena in the real-world environment, which are analog signals, to digital signals that can be processed by microprocessors for facilitating input processing. Sometimes the results processed and output by microprocessors also need to be converted to analog signals for subsequent applications. The former process is called analog-to-digital conversion (ADC), while the latter, digital-to-analog conversion (DAC). The ADC technologies can be categorized into integrative and comparative methods. The integrative methods are further categorized into the single-slope ADC and the dual-slope ADC; the comparative methods are further categorized into the counting ADC, the successive-approximation ADC, and the parallel-comparator ADC. These ADC circuits have their advantages and disadvantage, respectively. In general, it depends on the application scenarios for choosing the method.
There is an integration circuit in a general analog-to-digital converter. As shown in FIG. 1, an input signal IIN is integrated by an integration circuit comprising a capacitor C and an operational amplifier 12 for producing an integration signal at the output D of the operational amplifier 12. As shown in FIG. 2, this integration signal is a triangle-wave signal. A comparator 14 compares the integration signal to a reference signal Vref. If the integration signal is equal to or greater than the reference signal Vref, a comparison signal is produced. Thereby, the number of the comparison signal represents the number of the triangle-wave signal (the integration signal). A counter 16 is coupled to the output of the comparator 14 for counting the number of the comparison signal, namely, counting the number of the triangle-wave signal, for producing digital signals. Each comparison signal is further used as a reset signal RST1 for resetting the integration circuit and for re-integrating the input signal IIN and producing the integration signal. In other words, the next triangle-wave signal can be produced.
It is known from above that each time the comparator 14 compares the integration signal and the reference signal Vref and produces a comparison signal, the integration circuit has to be reset for producing the next integration signal. Thereby, for a 12-bit analog-to-digital converter, the counter 16 needs to count for 4095 times at most, and hence resetting the integration circuit for 4095 times at most as well. When the integration circuit according to the prior art is reset, the integral nonlinearity (INL) will be produced and accumulated. Consequently, this INL increases as the number of resets on the integration circuit increases and thus reducing the accuracy of the analog-to-digital converter. Thereby, how to reduce the INL has become a major subject currently in developing analog-to-digital converters.
Accordingly, the present invention provides an analog-to-digital converter, which can reduce the number of times for which the integration circuit is reset for reducing the INL. Hence, the accuracy of the analog-to-digital converter is enhanced and the problem described above can be solved.